NXP Semiconductors /MIMXRT1064 /PXP /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (IRQ_ENABLE)IRQ_ENABLE 0 (NEXT_IRQ_ENABLE)NEXT_IRQ_ENABLE 0 (ENABLE_LCD_HANDSHAKE)ENABLE_LCD_HANDSHAKE 0RSVD00 (ROT_0)ROTATE 0 (HFLIP)HFLIP 0 (VFLIP)VFLIP 0RSVD10 (ROT_POS)ROT_POS 0 (8X8)BLOCK_SIZE 0RSVD30 (EN_REPEAT)EN_REPEAT 0 (RSVD4)RSVD4 0 (CLKGATE)CLKGATE 0 (SFTRST)SFTRST

BLOCK_SIZE=8X8, ROTATE=ROT_0

Description

Control Register 0

Fields

ENABLE

Enables PXP operation with specified parameters

IRQ_ENABLE

Interrupt enable

NEXT_IRQ_ENABLE

Next command interrupt enable

ENABLE_LCD_HANDSHAKE

Enable handshake with LCD controller

RSVD0

Reserved, always set to zero.

ROTATE

Indicates the clockwise rotation to be applied at the output buffer

0 (ROT_0): ROT_0

1 (ROT_90): ROT_90

2 (ROT_180): ROT_180

3 (ROT_270): ROT_270

HFLIP

Indicates that the output buffer should be flipped horizontally (effect applied before rotation).

VFLIP

Indicates that the output buffer should be flipped vertically (effect applied before rotation).

RSVD1

Reserved, always set to zero.

ROT_POS

This bit controls where rotation will occur in the PXP datapath

BLOCK_SIZE

Select the block size to process.

0 (8X8): Process 8x8 pixel blocks.

1 (16X16): Process 16x16 pixel blocks.

RSVD3

Reserved, always set to zero.

EN_REPEAT

Enable the PXP to run continuously

RSVD4

Reserved, always set to zero.

CLKGATE

This bit must be set to zero for normal operation

SFTRST

Set this bit to zero to enable normal PXP operation

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